首页>
外国专利>
LOW JITTER LARGE FREQUENCY TUNING LC PLL FOR MULTI-SPEED CLOCKING APPLICATIONS
LOW JITTER LARGE FREQUENCY TUNING LC PLL FOR MULTI-SPEED CLOCKING APPLICATIONS
展开▼
机译:低抖动大频率调谐LC PLL,适用于多速率时钟应用
展开▼
页面导航
摘要
著录项
相似文献
摘要
ABSTRACT The subject innovation relates to systems and/or methodologies for generating a low jitter large frequency tuning LC-based phase-locked loop circuit for multi-speed clocking applications. In addition to a plurality of noise reduction features, the phase-locked loop includes programmable charge pump and loop filter that enable a wide loop bandwidth, a programmable VCO that enables a wide VCO frequency range and a per lane clock divider that further enables a wide PLL frequency range. Furthermore, an auto-calibration circuit ensures that the VCO included in the PLL receives the optimum current for noise reduction across the VCO frequency range.
展开▼