SYSTEMS AND METHODS USING PROGRAMMABLE FIXED FREQUENCY DIGITALLY CONTROLLED OSCILLATORS FOR MULTIRATE LOW JITTER FREQUENCY SYNTHESIS

摘要

The disclosure provides systems and methods for programmable fixed frequency digitally controlled oscillators for multirate low jitter frequency synthesis. The present invention utilizes a digital control element, such as a complex programmable logic device (CPLD) or field programmable gate array (FPGA), to monitor the frequency offset of a DCO with respect to one or more timing module (TM) references. The frequency offset is measured by aligning the phase of a DCO feedback divider to the phase of a reference divider, and then counting the number of pulses in the DCO between the falling edges of the feedback to determine a frequency error. Falling edge detection is used to determine a sign of the error. The digital control element then calculates a frequency correction based on a linear scaling factor to send a new control word to the DCO to reduce the frequency error.