A 0.6V Programmable Frequency Divider and Digitally Controlled Oscillator for use in a Digital PLL in the Subthreshold Region

摘要

A low power, synchronous, programmable frequency divider, and a digitally controlled oscillator (DCO) are presented in this paper. These circuits are designed for operation in the subthreshold region and are intended for use in a Phase-Locked Loop with application in low power Internet of Things devices. The frequency divider consists of a Johnson counter with configurable length and modified flip-flop clocking. The DCO is based on a variable length ring oscillator with a CMOS capacitive load to enable coarse and fine-tuning of the oscillation frequency. Both circuits operate with a 0. $6mathbf{V}$ supply. Post-layout simulations show that the programmable frequency divider consumes $3.7mu mathbf{W}$ for a 16MHz input, with possible division ratios that range from 2 to 11. It produces a 50% duty cycle output signal when fed with a clock signal with a duty cycle as low as 33%. The DCO consumes $14.8mu mathbf{W}{@}16mathbf{MHz}$ and outputs frequencies from 15kHz up to 16MHz according to post-layout simulations.