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Process charging and electrostatic damage protection in silicon-on-insulator technology

机译:绝缘体上硅技术中的过程充电和静电损坏保护

摘要

A SOI device features a conductive pathway between active SOI devices and a bulk SOI substrate. The conductive pathway provides the ability to sink plasma-induced process charges into a bulk substrate in the event of process charging, such as interlayer dielectric deposition in a plasma environment, plasma etch deposition, or other fabrication provides. A method is also disclosed which includes dissipating electrostatic and process charges from a top of a SOI device to the bottom of the device. The top and bottom of the SOI device may characterize a region of active devices and a semiconductor method respectively. The method further includes a single masking step to create seed regions for an epitaxial-silicon pathway.
机译:SOI器件的特征是有源SOI器件与体SOI衬底之间的导电路径。导电路径提供了在过程充电的情况下将等离子体诱导的过程电荷沉入块状衬底中的能力,例如在等离子体环境中的层间电介质沉积,等离子体蚀刻沉积或其他制造方法。还公开了一种方法,该方法包括将静电和工艺电荷从SOI器件的顶部耗散到该器件的底部。 SOI器件的顶部和底部可以分别表征有源器件的区域和半导体方法。该方法还包括单个掩膜步骤,以创建用于外延硅路径的种子区。

著录项

  • 公开/公告号US7755140B2

    专利类型

  • 公开/公告日2010-07-13

    原文格式PDF

  • 申请/专利权人 SANGWOO PAE;JOSE MAIZ;

    申请/专利号US20060593706

  • 发明设计人 JOSE MAIZ;SANGWOO PAE;

    申请日2006-11-03

  • 分类号H01L23/62;

  • 国家 US

  • 入库时间 2022-08-21 18:52:19

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