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Semiconductor integrated device, method of designing semiconductor integrated device, device for designing the same, and program

机译:半导体集成器件,设计半导体集成器件的方法,用于设计该器件的程序以及程序

摘要

A semiconductor integrated device has a wire layout structure such that SL1≦SL2SL3 wherein a minimum wiring space in a location where both of neighboring wires are fine wires is SL1, a minimum wiring space in a location where at least one of neighboring wires is a wide wire and the neighboring wires are at an equal potential is SL2, and a minimum wiring space in a location where at least one of neighboring wires is a wide wire and the neighboring wires are at an unequal potential is SL3.
机译:半导体集成器件具有线布局结构,使得SL 1 ≤SL 2 3 ,其中在的相邻线中的细线是SL 1 ,至少相邻线中的一根是宽线且相邻线处于等电位的位置的最小布线空间是SL 2 ,并且至少相邻的一根导线是宽导线且相邻的导线处于不等电位的位置的最小布线空间是SL 3。

著录项

  • 公开/公告号US7681168B2

    专利类型

  • 公开/公告日2010-03-16

    原文格式PDF

  • 申请/专利权人 TARO SAKURABAYASHI;

    申请/专利号US20050290533

  • 发明设计人 TARO SAKURABAYASHI;

    申请日2005-12-01

  • 分类号G06F17/50;

  • 国家 US

  • 入库时间 2022-08-21 18:50:23

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