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Code design and implementation improvements for low density parity check codes for multiple-input multiple-output channels

机译:用于多输入多输出通道的低密度奇偶校验码的代码设计和实现改进

摘要

Methods and systems for designing LDPC codes are disclosed. A method in accordance with the present invention comprises configuring a plurality (M) of parallel accumulation engines, accumulating a first information bit at a first set of specific parity bit addresses using the accumulation engines, increasing a parity bit address for each of the parity bit addresses by a pre-determined offset for each new information bit, accumulating subsequent information bits at parity bit addresses offset from the parity bit addresses by a pre-determined offset until an M+1 information bit is reached, accumulating the next M information bits at a second set of specific parity bit addresses using the parallel accumulation engines, increasing a parity bit address for each member of the second set of parity bit addresses by the pre-determined offset for each new information bit; and repeating accumulating and increasing the addresses until the information bits are exhausted.
机译:公开了用于设计LDPC码的方法和系统。根据本发明的方法包括配置多个(M)并行累加引擎,使用累加引擎在第一组特定奇偶校验位地址处累加第一信息比特,为每个奇偶校验位增加奇偶校验位地址每个新信息位的地址偏移一个预定的偏移量,将奇偶校验位地址的后续信息位从奇偶校验位地址偏移一个预定的偏移量,直到达到M + 1个信息位,然后在使用并行累加引擎的第二组特定奇偶校验位地址,将第二组奇偶校验位地址的每个成员的奇偶校验位地址增加每个新信息位的预定偏移量;并重复累加和增加地址,直到信息位耗尽为止。

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