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Code design and implementation improvements for low density parity check codes for multiple-input multiple-output channels

机译:用于多输入多输出通道的低密度奇偶校验码的代码设计和实现改进

摘要

Methods include configuring M parallel accumulation engines, accumulating a first information bit at a first set of specific parity bit addresses using the accumulation engines, increasing a parity bit address for each member of the first set of specific parity bit addresses by a pre-determined offset for each new information bit, accumulating subsequent information bits at parity bit addresses that are offset from the specific parity bit addresses by a pre-determined offset until an M+1 information bit is reached, accumulating the next M information bits at a second set of specific parity bit addresses using the accumulation engines, increasing a parity bit address for each member of the second set of specific parity bit addresses by the pre-determined offset for each new information bit; and repeating accumulating and increasing the addresses until the information bits are exhausted. Related systems are described.
机译:方法包括配置M个并行累加引擎,使用累加引擎在第一组特定奇偶校验位地址处累加第一信息位,将第一组特定奇偶校验位地址的每个成员的奇偶校验位地址增加预定的偏移量对于每个新的信息位,在相对于特定奇偶校验位地址偏移了预定偏移量的奇偶校验位地址处累积后续信息位,直到达到M + 1个信息位为止,在第二组信息处累积下一个M个信息位使用累积引擎的特定奇偶校验位地址,将第二组特定奇偶校验位地址的每个成员的奇偶校验位地址增加每个新信息位的预定偏移量;并重复累加和增加地址,直到信息位耗尽为止。描述了相关系统。

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