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Instruction issue control within a multi-threaded in-order superscalar processor
Instruction issue control within a multi-threaded in-order superscalar processor
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机译:多线程有序超标量处理器中的指令问题控制
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摘要
A multi-threaded in-order superscalar processor 2 is described having a fetch stage 8 within which thread interleaving circuitry 36 interleaves instructions taken from different program threads to form an interleaved stream of instructions which is then decoded and subject to issue. Hint generation circuitry 62 within the fetch stage 8 adds hint data to the threads indicating that parallel issue of an associated instruction is permitted with one of more other instructions.
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