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Semiconductor integrated circuit with full-speed data transition scheme for DDR SDRAM at internally doubled clock testing application
Semiconductor integrated circuit with full-speed data transition scheme for DDR SDRAM at internally doubled clock testing application
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机译:具有全速数据转换方案的半导体集成电路,用于内部双时钟测试应用中的DDR SDRAM
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摘要
The present invention provides a circuit and a method for the full speed testing of semiconductor memory chips. The invention provides a full-speed data transition scheme for double data rate (DDR) synchronous dynamic random access memory (SDRAM). For high speed or double speed stress testing of DDR SDRAM, the internal clock is double the speed of the external clock. During high speed test, this causes the data to be written or presented to the data path two times. This invention provides a circuit and method for creating a full-speed data transition scheme to overcome this double speed testing problem.
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