CIRCUIT FOR CONTROLLING DATA OUTPUT TIMING OF A SEMICONDUCTOR MEMORY APPARATUS FOR SELECTIVELY INPUTTING INPUT DATA OR A DELAY SIGNAL

摘要

PURPOSE: A circuit for controlling data output timing of a semiconductor memory apparatus is provided to reduce the number of switching unit by comprising a data output stage which is selectively inputted with input data or a delay signal.;CONSTITUTION: A first unit delay chain(100) delays input data and outputs the input data as a delay signal. A controller(200) generates a selection control signal and a control signal in response to a plurality of cas latency information signals. A data output stage(300) is selectively inputted with the input data or the delay signal in response to the selection control signal. The data output stage delays a signal inputted for the delay time according to the control signal, and outputs the signal as the output data. A first unit delay chain is serially connected to a plurality of unit delays.;COPYRIGHT KIPO 2010