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Achievable performance of sampled-data controllers with input and output delays

机译:具有输入和输出延迟的采样数据控制器可实现的性能

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Sampled-data systems often entail transport delays due to communication lags. In this paper we synthesize sampled-data controllers that account a priori for such delays. Our approach which accounts for measurement noise and intersample behavior, allows us to investigate the effect of delays on the achievable performance of sampled-data systems. Several examples are given to illustrate the effect of large delays on system performance. Depending upon measurement disturbance levels, numerical examples show that large delays may be incurred without a significant loss in performance.
机译:采样数据系统通常由于通信滞后而导致传输延迟。在本文中,我们合成了采样数据控制器,这些控制器先验地考虑了此类延迟。我们的方法考虑了测量噪声和样本间行为,使我们能够研究延迟对采样数据系统可实现性能的影响。给出了几个例子来说明大延迟对系统性能的影响。取决于测量干扰水平,数值示例表明,可能会导致较大的延迟,而不会显着降低性能。

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