首页> 外国专利> METHOD FOR FORMING A MICRO-PATTERN OF A SEMICONDUCTOR DEVICE, CAPABLE OF PREVENTING A VOID FROM OCCURRING WITHIN AN ETCH MASK PATTERN BY FORMING AN ETCHING MASK LAYER WITH A SPIN COATING PROCESS

METHOD FOR FORMING A MICRO-PATTERN OF A SEMICONDUCTOR DEVICE, CAPABLE OF PREVENTING A VOID FROM OCCURRING WITHIN AN ETCH MASK PATTERN BY FORMING AN ETCHING MASK LAYER WITH A SPIN COATING PROCESS

机译:形成半导体器件微图案的方法,该方法能够通过形成具有自旋涂层工艺的蚀刻掩模层来防止在蚀刻掩模图案内产生空隙

摘要

PURPOSE: A method for forming a micro-pattern of a semiconductor device is provided so that an expensive deposition apparatus is not needed by forming an etch mask layer using a spin coating process.;CONSTITUTION: A plurality of first etch mask patterns(130a) are formed on the top of a substrate. The plurality of first etch mask patterns are covered with a buffer layer(160). A plurality of second etch mask patterns(170a) are formed on the buffer layer between two of the first etch mask patterns among the plurality of first etch mask patterns. The substrate is exposed between the first etch mask pattern and the second etch mask pattern as a part of the buffer layer is removed. The exposed part of the substrate is etched to form a micro-pattern.;COPYRIGHT KIPO 2010
机译:目的:提供一种形成半导体器件微图案的方法,从而通过使用旋涂工艺形成蚀刻掩模层,从而无需昂贵的沉积设备。组成:多个第一蚀刻掩模图案(130a)在衬底的顶部上形成。多个第一蚀刻掩模图案被缓冲层(160)覆盖。在多个第一蚀刻掩模图案中的两个第一蚀刻掩模图案之间的缓冲层上形成多个第二蚀刻掩模图案(170a)。当去除缓冲层的一部分时,基板暴露在第一蚀刻掩模图案和第二蚀刻掩模图案之间。蚀刻衬底的暴露部分以形成微图案。; COPYRIGHT KIPO 2010

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