SERIAL-PARALLEL CONVERTING CIRCUIT CAPABLE OF ACTIVELY CONTROLLING THE TIMING BETWEEN DATA AND A SIGNAL WHICH ARE INPUTTED TO COMPONENTS

摘要

PURPOSE: A serial-parallel converting circuit is provided to prevent malfunction due to a timing margin shortage by controlling the resonance variation and the timing variation due to an external environment.;CONSTITUTION: A first register block(140) comprises a plurality of first registers for extracting parallel data to serial data in response to a first latching signal. A delay block(150) comprises a plurality of delaying elements which delays the parallel data outputted from a corresponding first register among the first registers by a predetermined time. A second register block(160) comprises a plurality of second registers which, in response to a second latching signal, latches the parallel data outputted from a corresponding delaying element among the delaying elements. A third register block(170) comprises a plurality of third registers for latching the parallel data outputted from a corresponding second register among the second registers in response to the first latching signal.;COPYRIGHT KIPO 2010