首页> 外国专利> ASYNCHRONOUS MULTI-BIT OTP MEMORY CELL AND AN ASYNCHRONOUS MULTI-BIT OTP MEMORY DEVICE, A PROGRAMMING METHOD AND A READ OUT METHOD OF THE SAME, CAPABLE OF REDUCING THE OCCUPANCY AREA OF A CELL ARRAY

ASYNCHRONOUS MULTI-BIT OTP MEMORY CELL AND AN ASYNCHRONOUS MULTI-BIT OTP MEMORY DEVICE, A PROGRAMMING METHOD AND A READ OUT METHOD OF THE SAME, CAPABLE OF REDUCING THE OCCUPANCY AREA OF A CELL ARRAY

机译:异步多比特otp存储器单元和异步多比特otp存储器装置,相同的编程方法和读出方法,能够减少单元阵列的占用面积

摘要

PURPOSE: An asynchronous multi-bit OTP memory cell and an asynchronous multi-bit OTP memory device are provided to reduce the whole layout by storing n-bit of data in one OTP cell.;CONSTITUTION: An OTP memory cell array(410) comprises at least two asynchronous multi-bit OTP memory cells. A controller(420) generates mode control signals for controlling a program mode or a read mode. A power switch circuit(430) switches a first voltage to a second voltage or a third voltage. A row decoder(440) decodes a row address signal. A word line driving circuit(450) drives at least two program word lines and at least read word lines. A column decoder(460) decodes a column address signal. A source line driver circuit(470) drives a corresponding source line. The source line switch enable circuit(480) generates a source line switch enable signal.;COPYRIGHT KIPO 2010
机译:目的:提供一种异步多位OTP存储单元和一种异步多位OTP存储设备,以通过在一个OTP单元中存储n位数据来减少整体布局。;构成:一种OTP存储单元阵列(410)包括:至少两个异步多位OTP存储单元。控制器(420)产生用于控制编程模式或读取模式的模式控制信号。电源开关电路(430)将第一电压切换为第二电压或第三电压。行解码器(440)解码行地址信号。字线驱动电路(450)驱动至少两条编程字线和至少读取字线。列解码器(460)解码列地址信号。源极线驱动器电路(470)驱动相应的源极线。源极线开关使能电路(480)产生源极线开关使能信号。; COPYRIGHT KIPO 2010

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