CMOS SRAM CAPABLE OF EASILY REDUCING THE SIZE OF A CELL AND IMPROVING THE ALIGNMENT MARGIN BETWEEN A GATE AND A BITLINE CONTACT NODE

摘要

PURPOSE: A CMOS SRAM is provided to improve the alignment margin between a gate and a bitline contact node by aligning the word line of a pair of transistors which are arranged in the outermost part in a line.;CONSTITUTION: A plurality of memory cells are arranged in each cell region. A first transistor pair is arranged on a semiconductor substrate(100). A second transistor pair is arranged on the first layer of the upper part of the semiconductor substrate. A third transistor pair is arranged on the upper part of the first layer. A word line includes the gates of the third transistor pair and is arranged in a first direction in a line. A bit line pair(240) is arranged in order to cross the word line in a second direction.;COPYRIGHT KIPO 2010