SEMICONDUCTOR MEMORY, SEMICONDUCTOR CHIP PACKAGE, TESTING METHOD FOR SEMICONDUCTOR CHIP PACKAGE

摘要

a plurality of test patterns generated by the test pattern generating circuit in the first memory chip mounted in the same package is output from the first memory chip to test the second memory chip is a heterogeneous. Therefore, when the memory chip is heterogeneous with the same package, it is possible to test the memory chip, even if the terminals of the memory chip is not connected to the external terminals of the system. Since it is necessary to form an external terminal in the system unnecessary. Therefore, it is possible to reduce the system cost. Since the test device generating a complex test pattern becomes unnecessary, it is possible to reduce the test cost. Since the test pattern generating circuit is configured by using a non-volatile logic, rather than prepare a test pattern, it is possible to conduct a test. Therefore, in order to configure the system user to buy the first and second memory chips can be easily tested.