FUNCTIONAL STRUCTURE OF PARALLEL ADDER FOR MULTIPLICATION, WHEREIN ARGUMENTS OFTERMS OF PARTIAL PRODUCTS ARE ARGUMENTS OF TERNARY NUMBER SYSTEM f(+1,0,-1) IN POSITIONAL-SIGN FORMAT THEREOF f(+/-) (VERSIONS)

摘要

FIELD: physics.;SUBSTANCE: in the first version each bit of the adder is in form of positive and conditionally negative summation channels, each of which has two NAND logical elements, AND logical element and two OR logical elements.;EFFECT: increased operation speed of the device.;2 cl, 11 dwg