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A method for fabricating a semiconductor device and semiconductor device with semiconductor regions, which have differently shaped channel regions

机译:一种用于制造半导体器件的方法和具有具有不同形状的沟道区的半导体区的半导体器件

摘要

By locally modifying the intrinsic stress of a dielectric layer laterally enclosing gate electrode structures of a transistor configuration formed in accordance with in-laid gate techniques, the charge carrier mobility of different transistor elements may individually be adjusted. In particular, in in-laid gate structure transistor architecture, NMOS transistors and PMOS transistors may receive a tensile and a compressive stress, respectively.
机译:通过局部地改变电介质层的固有应力,该电介质层横向地包围根据嵌入式栅技术形成的晶体管配置的栅电极结构,可以分别调节不同晶体管元件的电荷载流子迁移率。特别地,在嵌入式栅结构晶体管架构中,NMOS晶体管和PMOS晶体管可以分别接收拉应力和压应力。

著录项

  • 公开/公告号DE102004052617B4

    专利类型

  • 公开/公告日2010-08-05

    原文格式PDF

  • 申请/专利权人

    申请/专利号DE20041052617

  • 发明设计人

    申请日2004-10-29

  • 分类号H01L21/336;H01L29/78;

  • 国家 DE

  • 入库时间 2022-08-21 18:29:06

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