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LAYOUT INSPECTION APPARATUS, LAYOUT INSPECTION METHOD, AND LAYOUT INSPECTION PROGRAM

机译:布局检查装置,布局检查方法和布局检查程序

摘要

PROBLEM TO BE SOLVED: To provide a layout inspection apparatus for more accurately determining whether a printed board is laid out to reduce noise generated at an IC.;SOLUTION: A first path length calculating unit 12 of the layout inspection apparatus 100A calculates a first path length, which is the shortest conduction path from a power supply pin to a bypass capacitor, based on layout information stored in a storage unit 3. A second path length calculating unit 13 calculates a second path length, which is the shortest conduction path from the power supply pin to a power supply plane, based on the layout information. An evaluation value calculating unit 14 calculates an evaluation value regarding the size of the power supply plane, based on the layout information. A layout determining unit 17 determines that the layout is improper, if the first path length exceeds the second path length and if the evaluation value of the power supply plane exceeds a predetermined reference value.;COPYRIGHT: (C)2011,JPO&INPIT
机译:解决的问题:提供一种布局检查设备,用于更准确地确定是否布置印刷电路板以减少IC产生的噪声。解决方案:布局检查设备100A的第一路径长度计算单元12计算第一路径基于存储在存储单元3中的布局信息,它是从电源引脚到旁路电容器的最短传导路径的长度。第二路径长度计算单元13计算第二路径长度,该第二路径长度是从电源引脚到旁路电容器的最短传导路径。根据布局信息将电源引脚连接到电源平面。评估值计算单元14基于布局信息来计算关于电源平面的尺寸的评估值。如果第一路径长度超过第二路径长度并且电源平面的评估值超过预定参考值,则布局确定单元17确定布局不当。COPYRIGHT:(C)2011,JPO&INPIT

著录项

  • 公开/公告号JP2011086168A

    专利类型

  • 公开/公告日2011-04-28

    原文格式PDF

  • 申请/专利权人 SHARP CORP;

    申请/专利号JP20090239421

  • 发明设计人 MIZUGUCHI YUKINORI;MATSUMOTO TAKEHIDE;

    申请日2009-10-16

  • 分类号G06F17/50;H05K3/00;

  • 国家 JP

  • 入库时间 2022-08-21 18:20:46

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