首页>
外国专利>
Test pattern generation method for avoiding false testing in two-pattern testing for semiconductor integrated circuit
Test pattern generation method for avoiding false testing in two-pattern testing for semiconductor integrated circuit
展开▼
机译:避免半导体集成电路二图形测试中误测试的测试图形生成方法
展开▼
页面导航
摘要
著录项
相似文献
摘要
A test pattern generation method for determining if a combinational portion 17 is defective, by applying test patterns to a semiconductor integrated circuit 10 and comparing responses to the test patterns with expected responses, the method including: a first step of generating test patterns having logic bits for detecting defects and unspecified bits; a second step of selecting critical paths 19, 19a, 19b generated by the application of the test patterns; a third step of identifying critical gates on the critical paths 19, 19a, 19b; and a fourth step of determining unspecified bits so that a critical capture transition metric, which indicates the number of the critical gates whose states are changed, is reduced; wherein by reducing the critical capture transition metric, output delays from the critical paths 19, 19a, 19b are prevented, and thereby false testing can be avoided.
展开▼
机译:一种测试图案生成方法,用于通过将测试图案应用于半导体集成电路 10 B>并将对测试图案的响应与预期响应进行比较,来确定组合部分 17 B>是否存在缺陷,该方法包括:产生具有用于检测缺陷的逻辑位和未指定位的测试图案的第一步;选择通过应用测试模式生成的关键路径 19,19 B> a I> ,19 B> b I>的第二步;第三步,确定关键路径 19、19 B> a I> ,19 B> b I>上的关键门;第四步,确定未指定的比特,以减少指示状态改变的临界门的数量的临界捕获转变量度;其中,通过降低临界捕获过渡度量,可以从临界路径 19,19 B> a I> ,19 B> b I>输出延迟防止了错误检测,从而可以避免错误的测试。
展开▼