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Method of forming U-shaped floating gate with a poly meta-stable polysilicon layer

机译:用多亚稳多晶硅层形成U形浮栅的方法

摘要

A method of realizing a flash floating poly gate using an MPS process can include forming a tunnel oxide layer on an active region of a semiconductor substrate; and then forming a first floating gate on and contacting the tunnel oxide layer; and then forming second and third floating gates on and contacting the first floating gate, wherein the second and third floating gates extend perpendicular to the first floating gate; and then forming a poly meta-stable polysilicon layer on the first, second and third floating gates; and then forming a control gate on the semiconductor substrate including the poly meta-stable polysilicon layer. Therefore, it is possible to increase the surface area of the capacitor by a limited area in comparison with a flat floating gate. As a result, it is possible to improve the coupling ratio essential to the flash memory device and to improve the yield and reliability of the semiconductor device.
机译:一种使用MPS工艺实现快速浮置多晶硅栅极的方法可以包括:在半导体衬底的有源区上形成隧道氧化物层;以及在半导体衬底的有源区上形成隧道氧化物层。然后在隧道氧化层上形成第一浮栅并与之接触。然后在所述第一浮栅上形成第二浮栅和与所述第一浮栅接触的第二浮栅,所述第二浮栅和所述第三浮栅垂直于所述第一浮栅延伸。然后在第一,第二和第三浮栅上形成多亚稳态多晶硅层;然后在包括所述多亚稳多晶硅层的半导体衬底上形成控制栅。因此,与平坦的浮栅相比,可以将电容器的表面积增加有限的面积。结果,可以提高对于闪存器件必不可少的耦合比,并且可以提高半导体器件的成品率和可靠性。

著录项

  • 公开/公告号US7985670B2

    专利类型

  • 公开/公告日2011-07-26

    原文格式PDF

  • 申请/专利权人 TAE-WOONG JEONG;

    申请/专利号US20080121818

  • 发明设计人 TAE-WOONG JEONG;

    申请日2008-05-16

  • 分类号H01L21/3205;

  • 国家 US

  • 入库时间 2022-08-21 18:10:45

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