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METHOD FOR GENERATING MULTIPLE SERIAL BUS CHIP SELECTS USING SINGLE CHIP SELECT SIGNAL AND MODULATION OF CLOCK SIGNAL FREQUENCY
METHOD FOR GENERATING MULTIPLE SERIAL BUS CHIP SELECTS USING SINGLE CHIP SELECT SIGNAL AND MODULATION OF CLOCK SIGNAL FREQUENCY
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机译:利用单芯片选择信号和时钟信号频率的调制产生多个串行总线芯片选择的方法
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摘要
A system includes a serial bus having an electrical net for conveying a clock signal, and a master device and a plurality of slave devices coupled to the serial bus. The master device modulates a clock signal on its output on an electrical net according to first and second manners to select respective first and second of the slave devices. The first manner is distinct from the second manner. In alternate embodiments, the first and second manners are: (1) different frequencies of the clock signal; and (2) pulse trains on the clock signal with different predetermined numbers of clock edges prior to the assertion of a single slave select signal from the master device. In alternate embodiments: (1) each slave detects the first and second manners directly from the master; and (2) a distinct device detects the first and second manners from the master device and generates individual slave selects.
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