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Logic synthesis of multi-level domino asynchronous pipelines
Logic synthesis of multi-level domino asynchronous pipelines
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机译:多级多米诺骨牌异步管道的逻辑综合
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摘要
Methods and apparatus are described for optimizing a circuit design. A gate level circuit description corresponding to the circuit design is generated. The gate level circuit description includes a plurality of pipelines across a plurality of levels. Using a linear programming technique, a minimal number of buffers is added to selected ones of the pipelines such that a performance constraint is satisfied.
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