Comments on 'Dual-rail asynchronous logic multi-level implementation'

摘要

In this research communication, we comment on "Dual-rail asynchronous logic multi-level implementation" [Integration, the VLSI Journal 47 (2014) 148-159] by expounding the problematic issues, and provide some clarifications on delay-insensitivity, robust asynchronous logic, multi-level decomposition, and physical implementation. (C) 2015 Elsevier B.V. All rights reserved.