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Automated method and apparatus for very early validation of chip power distribution networks in semiconductor chip designs
Automated method and apparatus for very early validation of chip power distribution networks in semiconductor chip designs
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机译:用于非常早地验证半导体芯片设计中的芯片配电网络的自动化方法和装置
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摘要
Validation of full-chip power distribution networks can be performed very early, and continuously throughout the design cycle, to detect real physical power connection problems and enable early correction of power grid designs using early floor plan and power grid design data. Common power connection and distribution errors are automatically addressed as an integral part of the early chip floor planning and chip power build processes providing efficient solutions requiring no extra wiring resource to be implemented and reducing the runtime of required final full-chip physical design checks, and the overall design cycle.
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