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Layout structure in semiconductor memory device comprising global word lines, local word lines, global bit lines and local bit lines
Layout structure in semiconductor memory device comprising global word lines, local word lines, global bit lines and local bit lines
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机译:半导体存储器件中的布局结构,包括全局字线,局部字线,全局位线和局部位线
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摘要
A line layout structure and method in a semiconductor memory device having a hierarchical structure are provided. In a semiconductor memory device having a global word line and a local word line, and a global bit line and a local bit line, and individually disposing all of the global word line, the local word line, the global bit line and the local bit line at conductive layers among at least three layers; at least two of the global word line, the local word line, the global bit line and the local bit line are together disposed in parallel on one conductive layer. Signal lines constituting a semiconductor memory device are disposed in a hierarchical structure, whereby a semiconductor memory device advantageously having high integration, high speed and high performance may be obtained.
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