Method and system for pipelining saturated accumulation and other loops with loop-carried dependencies

摘要

Aggressive pipelining allows Field Programmable Gate Arrays (FPGAs) to achieve high throughput on many Digital Signal Processing applications. However, cyclic data dependencies in the computation can limit pipelining and reduce the efficiency and speed of an FPGA implementation. Saturated accumulation is an important example where such a cycle limits the throughput of signal processing applications. A reformulation of saturated addition as an associative operation permits a parallel-prefix calculation to be used to perform saturated accumulation at any data rate supported by the device. The method may be extended to other operations containing loops with one or more loop-carried dependencies.