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Method for checking constraints equivalence of an integrated circuit design
Method for checking constraints equivalence of an integrated circuit design
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机译:检验集成电路设计约束等效性的方法
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摘要
The equivalence of two or more constraint files of an integrated circuit (IC) design are checked. The comparison is performed between files at the same stage of design, files that correspond to different stages of the design flow, or between top-level and block-level constraint files.
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