Clocking scheme for efficient digital noise reduction in mixed-signal systems-on-chip

摘要

In one embodiment of the present invention, a clock generator circuit receives a clock signal having a period. The clock signal is employed by a digital circuit that is resident on the same substrate as an analog circuit, the digital circuit generates disturbance climaxes at clock edges that propagate through the substrate to the analog circuit. A clock generator circuit generates a plurality of clock signals, with each clock signal having a unique rate, wherein during a temporal gap, defined by the time between a last disturbance climax and a next sampling time of the clock signal, clock edges of any of the plurality of clock signals are avoided.