Synthesis of Optimal Clocking Schemes for Digital Systems

摘要

This research examined some important problems of synthesis of digital systems. In particular, the focus was on some specific design decisions which produce a register-transfer hardware implementation of a digital system with near optimal speed under certain design constraints and desired optimization goals. Consideration was given to optimizing the speed of an already designed system by reconfiguring the interconnections of the hardware modules. The final report gives a brief overview of high-performance control styles of digital systems and then focus on the area of speed optimization of digital systems with centralized controllers.