HDL CO-SIMULATION IN A HIGH-LEVEL MODELING SYSTEM

摘要

Method and apparatus for simulating operations of a circuit design thatincludes high-level components and HDL components. The high-level componentsof the design are simulated in a high-level modeling system (HLMS), and theHDL components of the design are simulated with an HDL simulator. Data valuesare converted from a data type of the HLMS to a logic vector compatible withthe HDL simulator for each data value to be input to the HDL simulator, and alogic vector is converted from the HDL simulator to a data value of a datatype compatible with the HLMS for each logic vector output from the HDLsimulator. Events are scheduled for input to the HDL simulator as a functionof the time of HLMS events and a maximum response time of the HDL components.