Memory cell and wordline driver for embedded dram in asic process

摘要

The present invention relates to a voltage boost circuit comprising a p-channel FET capacitor having a gate forming a top plate and source and drain forming a bottom plate, an output node for providing a boosted output voltage connected to the top plate. In order to provide a charge storage structure, which avoids charge leakage from the storage capacitor to the substrate, eliminates the requirement for a continuous voltage VBB and is thus highly suitable for use in ASICs, the present invention is characterized by a first p-channel FET having its source connected to a voltage source VDD and its drain connected to the top plate, a second p-channel FET having its drain connected to the top plate and a third p-channel FET having its drain connected to a gate of the second FET and its gate to ground, in inverter having its output connected to the bottom plate of the capacitor and its input to the source of the third FET, means for applying a signal to the first FET to cause it to conduct and thus raise the output node to VDD and to charge the top plate to VDD, means for ceasing applying a first signal to the gate of the first FET and applying a second signal to the source of the second FET to bring the top plate and output node to the ground and for applying a third signal to the source of the third FET, and for applying the third signal through the inverter to the bottom plate of the capacitor following a delay through the inverter lowering the voltage at the top plate of the capacitor below VSS to a negatively boosted voltage -Vboost.