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METHOD AND SYSTEM FOR IMPROVING THE MANUFACTURABILITY OF INTEGRATED CIRCUITS

机译:改善集成电路可制造性的方法和系统

摘要

At a particular stage in design of an integrated circuit, DFM improvements are identified which might conflict with design requirements applicable during a subsequent stage in the design flow. These DFM improvements are reserved that is, they are not implemented right away. However, an instance of a DFM-optimized version of this portion of the design is generated, characterized and stored. Meta information is associated with the reserved DFM improvements, for example locations in the design which correspond to the reserved DFM improvements are tagged. If, after the subsequent stage in the design flow, processing of the meta-information (tags) shows that the reserved DFM improvement does not actually conflict with the potentially-conflicting design requirement, the corresponding reserved DFM improvement is implemented, for example, by swapping-in the stored instance of the DFM-optimized version of this portion of the design.
机译:在集成电路设计的特定阶段,将确定DFM改进,这些改进可能与在设计流程的后续阶段中适用的设计要求相冲突。这些DFM改进是保留的,也就是说,它们不会立即实施。但是,将生成,表征和存储该设计部分的DFM优化版本的实例。元信息与保留的DFM改进相关联,例如,在设计中标记了与保留的DFM改进相对应的位置。如果在设计流程的后续阶段之后,对元信息(标签)的处理显示保留的DFM改进实际上与潜在冲突的设计要求没有冲突,则可以通过以下方式实现相应的保留的DFM改进:交换设计这一部分的DFM优化版本的存储实例。

著录项

  • 公开/公告号EP1820130B1

    专利类型

  • 公开/公告日2011-09-14

    原文格式PDF

  • 申请/专利权人 FREESCALE SEMICONDUCTOR INC.;

    申请/专利号EP20040804495

  • 发明设计人 RIVIERE-CAZEAUX LIONEL;

    申请日2004-11-30

  • 分类号G06F17/50;

  • 国家 EP

  • 入库时间 2022-08-21 17:58:51

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