SUCCESSIVE APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTER WITH INTEGRAL NON-LINEARITY CORRECTION

摘要

Integral non-linearity (INL) error in a successive approximation register (SAR) analog- to-digital converter (ADC) (10) is reduced by providing correction capacitors (HB) each having a first terminal connected to a conductor (13) which is also connected to one terminal of the capacitors of a CDAC (HA) and to an input of a comparator (5) of the SAR ADC. Stored INL error information (18A) is utilized to control switches coupled to second terminals of the correction capacitors to selectively couple them to either a ground voltage (GND) or a reference voltage (VREF) in response to the stored INL error information so as to reduce the INL errors.