NON-OVERLAPPING CLOCK GENERATOR FOR GENERATING A UNIFORM NON-OVERLAPPING SECTION

摘要

PURPOSE: A non-overlapping clock generator is provided to regularly generate a phase-delayed clock by supplying a fixed non-overlapping section regardless of the variation of P.V.T(Process,Supply voltage,Temperature). ;CONSTITUTION: A D flip-flop(DFF) comprises a clock terminal(CLK), an input terminal(D), a first output terminal(Q), and a second output terminal(Q'). A first clock(S1) is applied to the clock terminal and the input terminal is connected with the second output terminal. A NAND gate(ND) includes two input terminals. A first input terminal(IN1) is connected with the first output terminal of the D flip-flop and a second clock(S2) is applied to a second input terminal(IN2). The output of the NAND gate is applied to an inverter(INV).;COPYRIGHT KIPO 2011