STACKED MEMORY DEVICE HAVING AN INTER-CHIP CONNECTION UNIT, A MEMORY SYSTEM INCLUDING THE SAME, AND A METHOD OF COMPENSATING DELAY TIME OF TRANSMISSION LINES, HAVING A MATCHING STRUCTURE OF THE IMPEDANCE IN TRANSMISSION LINE

摘要

PURPOSE: A stacked memory device having an inter-chip connection unit, a memory system including the same, and a method of compensating delay time of transmission lines are provided to automatically select a chip without using a chip identification signal.;CONSTITUTION: A first transmission line is combined between a first chip connecting unit(130). The first transmission line is formed within a first memory chip(110). The first chip connecting unit is combined between the first memory chip and the second memory chip(120). The second transmission line is combined with a chip connecting unit(140). The second transmission line is formed within the first memory chip. A logic circuit(114) is formed within the first memory chip. A logic circuit compares a first signal(SIG1) and a second signal(SIG2).;COPYRIGHT KIPO 2012