ALL-DIGITAL CLOCK DATA RECOVERY HAVING AN ADAPTIVE PROPORTIONAL GAIN CONTROL

摘要

The all-digital clock data recovery circuit (ADCDR) according to the present invention monitors the pattern of the up / down (UP / DN) signal output by the phase detector, and counts the number of repetitions when the up / down is repeated. If the selected number is exceeded, the step size of proportional gain is decreased, and if the polarity of the phase error is not changed by continuing up or down, the duration is counted and if it is more than the selected number, the step size of proportional gain is increased. The proportional gain step size is adjusted according to the up / down signal pattern.