首页> 外国专利> METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE WITH A BURIED GATE CAPABLE OF PREVENTING A SHORT BETWEEN THE BURIED GATE AND A CONTACT PLUG

METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE WITH A BURIED GATE CAPABLE OF PREVENTING A SHORT BETWEEN THE BURIED GATE AND A CONTACT PLUG

机译:制造具有能够防止埋入式浇口和接触塞之间短路的埋入式浇口的半导体装置的方法

摘要

PURPOSE: A method for manufacturing a semiconductor device with a buried gate is provided to prevent a buried gate from being exposed in a contact etching process by implanting nitrogen ions to a gate insulation layer exposed to the outside of the buried gate.;CONSTITUTION: A trench is formed by etching a substrate(21). A gate insulation layer(23A) is formed on the surface of the substrate and the trench. A buried gate(24) is formed by partially filling the trench. An etch barrier layer(26) is formed by post-processing the gate insulation layer. An interlayer dielectric layer(27) is formed on the front surface with the etch barrier layer. A contact hole(28) is formed by etching the interlayer dielectric layer and the etch barrier layer.;COPYRIGHT KIPO 2012
机译:目的:提供一种用于制造具有掩埋栅的半导体器件的方法,以通过向暴露于掩埋栅外部的栅绝缘层注入氮离子来防止掩埋栅在接触蚀刻工艺中暴露。通过蚀刻衬底(21)形成沟槽。在衬底和沟槽的表面上形成栅绝缘层(23A)。通过部分填充沟槽来形成掩埋栅(24)。通过对栅极绝缘层进行后处理来形成蚀刻阻挡层(26)。在具有蚀刻阻挡层的前表面上形成层间电介质层(27)。通过蚀刻层间介电层和蚀刻阻挡层形成接触孔(28)。; COPYRIGHT KIPO 2012

著录项

  • 公开/公告号KR20110118981A

    专利类型

  • 公开/公告日2011-11-02

    原文格式PDF

  • 申请/专利权人 HYNIX SEMICONDUCTOR INC.;

    申请/专利号KR20100038414

  • 发明设计人 CHO JUN HEE;

    申请日2010-04-26

  • 分类号H01L21/336;H01L29/78;

  • 国家 KR

  • 入库时间 2022-08-21 17:50:50

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