Circuit which allows read and write operation to a register file bit cell array at a lower supply voltage without increasing the area.

摘要

A register file is coupled to logic that reduces the contention between the NMOS devices and the PMOS devices in each bit cell of the register file during write and/or read operations, and hence the register file is able to operate at a lower minimum voltage. In one embodiment, the write bit line 150 (or data line) is directly connected to the gate of a PMOS switching device 342, which connects the power supply 360 to a first internal supply bus VCC_A, when write bit line is low. The complement write bit line 155 (or data line) is directly connected to the gate of PMOS device 346, and connects supply 360 to a second internal supply bus VCC_B, when complement write bit line is low. The first supply buses VCC_A , provides the supply voltage for one half of each of the cross coupled logic gates 111 forming the memory cells, whilst the second supply bus VCC_B provides power for the other half 112 of each of the cells. Hence, depending on the state of the write bit data line, in write mode, only one half of the bit cells are directly connected to the supply 360, by means of PMOS switches 342,346. In order to prevent the unconnected half of the memory cells from floating, an equalizer circuit, (or clamp) comprising of two weak PMOS devices in series, 352,350 connects the first and second supply busses VCC_A and VCC_B together. Also in the same embodiment, a read retention circuit is included, which connects a write enable signal 380 to the gate of two PMOS devices 344, 348, allowing the potential of both VCC_A and VCC_B to return to that of the power supply 360, during the read or inactive operation.