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Cell library verification program, recording medium, cell library verification device in which the program is recorded, and the cell library verification method

机译:单元库验证程序,记录介质,记录该程序的单元库验证装置以及单元库验证方法

摘要

PROBLEM TO BE SOLVED: To guarantee quality of a composite circuit by improving a use rate of a composite cell when performing circuit composition optimum in delay.;SOLUTION: On a development side of a self library, the quality of storage contents of the self library is decided without depending on a benchmark circuit, and the storage contents are optimized according to a decision result thereof. Specifically, when a delay value of the composite cell held in the self library is larger than a delay value of a logic circuit equivalent to a function of the composite cell, comprising a combination of simple cells, a dimension of a transistor of the composite cell is changed to perform optimization to make the delay value of the composite cell not more than the delay value of the logic circuit.;COPYRIGHT: (C)2009,JPO&INPIT
机译:解决的问题:在延迟中执行最佳电路组成时,通过提高复合单元的使用率来保证复合电路的质量。解决方案:在自库的开发方面,自库的存储内容的质量在不依赖基准电路的情况下进行判定,并且根据其判定结果来优化存储内容。具体地,当保存在自库中的复合单元的延迟值大于等效于包括简单单元的组合的复合单元的功能的逻辑电路的延迟值时,复合单元的晶体管的尺寸更改以执行优化,以使复合单元的延迟值不超过逻辑电路的延迟值。;版权所有:(C)2009,JPO&INPIT

著录项

  • 公开/公告号JP5050865B2

    专利类型

  • 公开/公告日2012-10-17

    原文格式PDF

  • 申请/专利权人 富士通セミコンダクター株式会社;

    申请/专利号JP20080004201

  • 发明设计人 樋口 博之;

    申请日2008-01-11

  • 分类号G06F17/50;

  • 国家 JP

  • 入库时间 2022-08-21 17:42:16

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