Optimization of the SRAM efficiency which covers the voltage or process range which used the self timing type calibration of the local clock formation vessel and is expanded

摘要

Topic The method of operating the memory array like static random access memory (SRAM) making use of the clock pulse which is formed locally, is offered.Solutions The delay circuit, has with the fixed delay route and the level converter of low voltage level and the adjustment possible delay route of high voltage level. Fixed delay route includes the invertor chain, adjustment possible delay route includes the series connection delay element which is connected to circuit output selectively. In the use for the local clock buffer of static random access memory (SRAM), low voltage level is something of the local clock buffer, high voltage level is something of SRAM. These voltage are times when it changes according to dynamic voltage scaling need the re-calibration of adjustment possible delay route. Until the output whose simultaneous reading operation is correct is returned, it is possible to calibrate adjustment possible delay route by simulating the fluctuation of the delay which accompanies the change of power source by making the reading access time of SRAM array increase gradually, or, making use of duplication SRAM route. Selective figure Figure 2