Programmable digital signal processor with clustered SIMD micro-architecture including short complex multiplier and independent vector load unit

摘要

Processor comprises a complex computing unit and accelerator units. Each of the accelerator units may perform dedicated functions of one or more. The processor core includes an integer execution unit capable of executing integer instructions. Complex computing unit may include a complex computational logic unit execution pipeline, the execution pipeline can include a vector load unit and the data one or more paths. Data paths each include a short complex multiplier / accumulator unit, the complex data value, the complex multiplier / accumulator unit number, including - - {i 0, + /} {0, + / 1} + I may be configured to multiply the values ​​in a group of. Can be fetched with each clock cycle the complex data item by the vector load unit, complex data items are used in the data path of one of the complex computational logic unit execution pipeline.