A Hardwareunit generation algorithm for packed SIMD type functional units of digital signal processor cores

摘要

Consider to synthesize a processor core with packed SIMD type instructions by a hardware/software cosynthesis system. The system is required to configure functional units executing packed SIMD type instructions and obtain the area and delay of the functional units to evaluate the synthesized processor core. This paper proposes a hardware unit generation algorithm for packed SIMD type functional units. Given a set of instructions to be executed by a hardware unit and constraints for area and delay of the hardware unit the proposed algorithm extracts a set of sub-functions to be required by the hardware unit and generates more than one architecture candidates for the hardware unit. The algorithm also outputs the estimated area and delay of each of the generated hardware units. The execution time of the proposed algorithm is very short and thus it can be easily incorporated into the processor core synthesis system. Experimental results for packed SIMD type functional units demonstrate effectiveness and efficiency of the algorithm.