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Method, logic device and system for calculating circuit jitter, and method, logic device and system for synthesizing circuit clock tree

机译:用于计算电路抖动的方法,逻辑设备和系统,以及用于合成电路时钟树的方法,逻辑设备和系统

摘要

In one embodiment, a method for computing jitter in a clock tree includes dividing a clock tree into a plurality of stages and computing jitter in one or more of the stages according to a model of at least a portion of a circuit associated with the clock tree. The model includes a representation of each source of jitter in the circuit. The method also includes, to compute jitter associated with a path or a pair of paths in the clock tree, statistically combining the jitter in each of the stages of the path or the pair of paths in the clock tree with each other. In one embodiment, to efficiently compute jitter and to achieve zero clock skew, a method synthesizes a symmetrical clock tree of a circuit in which corresponding stages in all paths from a root of the clock tree to sinks of the clock tree exhibit approximate electrical equivalence to each other.
机译:在一个实施例中,一种用于计算时钟树中的抖动的方法包括:将时钟树划分为多个级,并且根据与时钟树相关联的电路的至少一部分的模型来计算一个或多个级中的抖动。 。该模型包括电路中每个抖动源的表示。该方法还包括,为了计算与时钟树中的路径或一对路径相关联的抖动,将时钟树中的路径或路径对中的每个阶段的抖动统计地彼此组合。在一个实施例中,为了有效地计算抖动并实现零时钟偏斜,一种方法合成了电路的对称时钟树,其中从时钟树的根部到时钟树的宿的所有路径中的相应级都具有与彼此。

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