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Simulation model of BT instability of transistor
Simulation model of BT instability of transistor
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机译:晶体管BT不稳定性仿真模型
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摘要
A simulation model of BT instability of a transistor in a semiconductor integrated circuit, wherein a bias condition of at least one terminal among the drain terminal, the source terminal and the substrate terminal of the transistor is set up as an independent bias condition from other terminals; and then a model parameter of the transistor is changed in the set bias condition.
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