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Reducing critical cycle delay in an integrated circuit design through use of sequential slack
Reducing critical cycle delay in an integrated circuit design through use of sequential slack
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机译:通过使用顺序松弛来减少集成电路设计中的关键周期延迟
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摘要
A method is provided that includes: determining a minimum clock cycle that can be used to propagate a signal about the critical cycle in a circuit design; wherein the critical cycle is a cycle in the design that has a highest proportionality of delay to number of registers; determining for a circuit element in the circuit design, sequential slack associated with the circuit element; wherein the sequential slack represents a minimum delay from among respective maximum delays that can be added to respective structural cycles of which the circuit element is a constituent, based upon the determined limit upon clock cycle duration; using the sequential slack to ascertain sequential optimization based design flexibility throughout multiple stages of a design flow.
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