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Scalable flash EEPROM memory cell with floating gate spacer wrapped by control gate and method of manufacture
Scalable flash EEPROM memory cell with floating gate spacer wrapped by control gate and method of manufacture
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机译:具有由控制栅包裹的浮栅隔离层的可扩展闪存EEPROM存储单元及其制造方法
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摘要
A polysilicon spacer as a floating gate of a Flash memory device. An advantage of such spacer structure is to reduce a cell size, which is desirable for state-of-the-art Flash memory technology. In a preferred embodiment, the floating gate can be self-aligned to a nearby and/or within a vicinity of the select gate of the cell select transistor. In a preferred embodiment, the present invention preserves a tunnel oxide layer after the removal, using dry etching, a polysilicon spacer structure on the drain side of the select transistor gate. More preferably, the present method provides for a certain amount of tunnel oxide to remain so as to prevent the active silicon area in the drain region of the memory cell from being etched by the dry etching gas.
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