首页>
外国专利>
Apparatus for implementing processor bus speculative data completion
Apparatus for implementing processor bus speculative data completion
展开▼
机译:用于实现处理器总线推测性数据完成的设备
展开▼
页面导航
摘要
著录项
相似文献
摘要
A method, and apparatus are provided for implementing processor bus speculative data completion in a computer system. A memory controller in the computer system sends uncorrected data from a memory to a processor bus. The memory controller also applies the uncorrected data to error correcting code (ECC) checking and correcting circuit. When a single bit error (SBE) is detected, corrected data is sent to the processor bus a predefined number of cycles after the uncorrected data.
展开▼