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Logic circuit, logic circuit design method, logic circuit design system, and logic circuit design program

机译:逻辑电路,逻辑电路设计方法,逻辑电路设计系统和逻辑电路设计程序

摘要

A latch conversion circuit which is to be added to a basic logic circuit to obtain a latch circuit having an extremely small through delay amount is prepared in advance. Moreover, provided is means for obtaining a latch circuit position whereat the shifting of the clock edge, such as skew or jitter, can be absorbed to the maximum extent possible, and for forming a latch circuit by adding the latch conversion circuit to the basic logic circuit located at the obtained point. Accordingly, a latch circuit which is not, to the extent possible, affected by skew or jitter can be designed.
机译:预先准备将被添加到基本逻辑电路以获得具有极小的通过延迟量的锁存电路的锁存转换电路。此外,提供了一种用于获得锁存器电路位置的装置,在该装置中可以最大程度地吸收时钟边缘的偏移(例如偏斜或抖动),并且通过将锁存器转换电路添加到基本逻辑来形成锁存器电路。电路位于获得的点。因此,可以设计不受歪斜或抖动影响的锁存电路。

著录项

  • 公开/公告号US8065645B2

    专利类型

  • 公开/公告日2011-11-22

    原文格式PDF

  • 申请/专利权人 SHIGETO INUI;YASUHIKO HAGIHARA;

    申请/专利号US20070754410

  • 发明设计人 SHIGETO INUI;YASUHIKO HAGIHARA;

    申请日2007-05-29

  • 分类号G06F9/455;G06F17/50;

  • 国家 US

  • 入库时间 2022-08-21 17:26:10

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