首页> 外国专利> Systems and methods for coalescing memory accesses of parallel threads

Systems and methods for coalescing memory accesses of parallel threads

机译:用于合并并行线程的内存访问的系统和方法

摘要

One embodiment of the present invention sets forth a technique for efficiently and flexibly performing coalesced memory accesses for a thread group. For each read application request that services a thread group, the core interface generates one pending request table (PRT) entry and one or more memory access requests. The core interface determines the number of memory access requests and the size of each memory access request based on the spread of the memory access addresses in the application request. Each memory access request specifies the particular threads that the memory access request services. The PRT entry tracks the number of pending memory access requests. As the memory interface completes each memory access request, the core interface uses information in the memory access request and the corresponding PRT entry to route the returned data. When all the memory access requests associated with a particular PRT entry are complete, the core interface satisfies the corresponding application request and frees the PRT entry.
机译:本发明的一个实施例阐述了一种用于高效且灵活地对线程组执行合并的存储器访问的技术。对于为线程组提供服务的每个读取应用程序请求,核心接口都会生成一个未决请求表(PRT)条目和一个或多个内存访问请求。核心接口基于内存访问地址在应用程序请求中的分布来确定内存访问请求的数量和每个内存访问请求的大小。每个内存访问请求都指定了内存访问请求所服务的特定线程。 PRT条目跟踪未决内存访问请求的数量。随着内存接口完成每个内存访问请求,核心接口将使用内存访问请求中的信息和相应的PRT条目来路由返回的数据。当与特定PRT条目关联的所有内存访问请求完成时,核心接口将满足相应的应用程序请求并释放PRT条目。

著录项

相似文献

  • 专利
  • 外文文献
  • 中文文献
获取专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号